1. Field of the Invention
The present invention relates to a power supply circuit, and particularly, to a power supply circuit with a charge pump.
2. Description of the Related Art
A conventional power supply circuit stepping up the power supply voltage (refer to Japanese published unexamined patent application 2000-166220, for example), will be described. Referring to FIG. 11, a power supply circuit 100 comprises a charge pump 10 outputting stepped-up voltage by switch operation in synchronization with clock signal CLK1, and a regulator 20 regulating the output of the charge pump 10 by skipping the pulses of the clock signal CLK1 according to the output voltage of the charge pump 10.
As the example in FIG. 12 shows, the charge pump 10 comprises capacitors C1, C2 and the switches SW1, SW2, SW3 and SW4. The switch SW1, capacitor C1 and the switch SW2 are connected in series between VDD and ground terminal Gnd. The switch SW3 is connected between the power supply terminal VDD and the connection points of capacitor C1 and switch SW2. The switch SW4 and capacitor C2 are connected in series between ground terminal Gnd and the connection points of switch SW1 and capacitor C1, and the serial connection point is connected to the output terminal Vout as the output of the charge pump 10. The switches SW1 and SW2 and switches SW3 and SW4 are ON/OFF controlled complementarily by the input clock signal CLK2.
The step-up operation of the charge pump 10 will be described. First, by inputting the “H” level clock signal CLK2, the switches SW1 and SW2 turn ON and the switches SW3 and SW4 turn OFF, and the capacitor C1 is charged by the power supply voltage VDD. Then, by the input of the “L” level clock signal CLK2, the switches SW1 and SW2 turn OFF, the switches SW3 and SW4 turn ON, and the capacitor C2 is charged with voltage being equal to the power supply voltage VDD plus the voltage charged in capacitor C1. By repeating this ON/OFF control, stepped up voltage is output to the output of the charge pump 10. If ON/OFF is controlled such that the charging voltage of capacitors C1 and C2 saturate, the stepped up voltage, which is double that of the power supply voltage VDD, is output to the output of the charge pump 10. In this power supply circuit 100, the pulse of the clock signal CLK2 is skipped (set to “H” level in this example) for a predetermined time so that the recharging voltage of the capacitor C2 does not become saturated, and the step-up operation is stopped by controlling the switches SW3 and SW4 to OFF to output the stepped-up voltage lower than double of the power supply voltage VDD to the output of the charge pump 10.
As FIG. 11 shows, the regulator 20 comprises a voltage dividing circuit 21, comparator 22, reference voltage source 23 and NAND circuit 24. The voltage dividing circuit 21 further comprises the voltage dividing resistors R1 and R2 which are connected in series between the output of the charge pump 10 and the ground terminal Gnd, and outputs the divided voltage Vd from the voltage dividing point Pd. In the comparator 22, the voltage dividing point Pd is connected to the inversion input, and the reference voltage source 23 is connected to the non-inversion input for comparing the divided voltage Vd with the reference voltage Vref, and the comparator output Vc becomes “L” level if the divided voltage Vd is higher than the reference voltage Vref, and becomes “H” level if the divided voltage Vd is lower. The comparator 22 has hysteresis by the peripheral circuit, which is not illustrated, so that the output Vc does not become “H” level or “L” level at a high frequency where the frequency is unstable. In the NAND circuit 24, the clock signal input terminal CLK1 is connected to one input, and the output of the comparator 22 is connected to the other input, the NAND operation is performed on the first clock signal CLK1 from the clock signal input terminal CLK1 and the comparator output Vc, and the result is supplied to the clock input of the charge pump 10 as the second clock signal CLK2.
Now the operation of the power supply circuit 100 with the above configuration will be described with reference to FIGS. 13A-13D. The power supply voltage VDD, such as VDD=3V, is supplied to the power supply terminal VDD by a DC power supply, such as a battery. The clock signal CLK1, such as 10 kHz, is supplied to the clock signal input terminal CLK1, as shown in FIG. 13A. The voltage dividing resistors R1 and R2 of the voltage dividing circuit 21 are set to R1/R2=1, for example, the output potential of the charge pump 10 is divided at the voltage dividing point Pd of the voltage dividing circuit 21, and the divided voltage Vd thereof is compared with the reference voltage Vref, such as Vref=2.5V, by the comparator 22. It is assumed that the comparator 22 has a hysteresis width of Vref±Vw/2. At the time T1, Vd<Vref+Vw/2, as shown in FIG. 13D, and the output voltage Vc of the comparator 22 is “H” level, as shown in FIG. 13B. The NAND operation is performed by the NAND circuit 24 on this “H” level and the clock signal CLK1, and as FIG. 13C shows, the CLK1 bar, which is the clock signal CLK1 is inverted, is output from the NAND circuit 24 as the clock signal CLK2. The charge pump 10 continues the step-up operation in accordance with the input of the clock signal CLK2=CLK1 bar until Vd>Vref+Vw/2 is established, that is until the output terminal voltage Vout exceeds the regulated voltage Vout=Vref×(1+R1/R2)=2.5×(1+1)=5V.
At the time T2, when Vd>Vref+Vw/2 is established, as shown in FIG. 13D, the output voltage Vc of the comparator 22 changes from “H” level to “L” level, as shown in FIG. 13B. The NAND operation is performed in the NAND circuit 24 on this “L” level and the clock signal CLK1, and the pulses of the clock signal CLK1 are skipped and the “H” level is output from the NAND circuit 24 as the clock signal CLK2, as shown in FIG. 13C. The charge pump 10 stops the step-up operation in response to the input of the clock signal CLK2 of “H” level until Vd<Vref−Vw/2 is established, that is until the output terminal voltage Vout becomes lower than the regulated voltage Vout=Vref×(1+R1/R2)=5V.
At the time T3, when Vd<Vref−Vw/2 is established, as shown in FIG. 13D, the output voltage Vc of the comparator 22 is inverted from “L” level to “H” level, as shown in FIG. 13B. By this “H” level, the CLK1 bar, which corresponds to the inverted clock signal CLK1, is output from the NAND circuit 24 as the clock signal CLK2, just like the case of the time T1, and the charge pump 10 continues the step-up operation until Vd>Vref+Vw/2 is established by the input of the clock signal CLK2=CLK1 bar. By repeating these operations, the power supply circuit 100 operates such that the divided voltage Vd comes within the hysteresis of Vref±Vw/2, as shown in FIG. 13D, and the regulated voltage Vout=Vref×(1+R1/R2)=2.5×(1+1)=5V is output to the output terminal Vout.
In the conventional power supply circuit 100, the comparator 22 has hysteresis so that the output Vc of the comparator 22 does not become “H” level or “L” level at a high and unstable frequency. This hysteresis must be sufficient to compensate the high and unstable frequency output from the comparator 22 due to the fluctuation of the load connected to the output terminal Vout. It has now been discovered that, when increasing the hysteresis, however, if the output terminal voltage Vout exceeds the desired value, the comparator 22 stops the step-up operation of the charge pump until the output terminal voltage Vout drops from the desired value by the amount of the hysteresis. As a result, the ripple of the output terminal voltage Vout increases.